The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2001-44052 filed on Jul. 21, 2001, which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection units for integrated circuits and, more specifically, to ESD protection units made of silicon-controlled rectifiers (SCRs) operable in low power integrated circuits.
2. Description of the Art
Semiconductor integrated circuits fabricated by CMOS (complementary metal-oxide-semiconductor) techniques are very sensitive to an ESD, which may be caused by contact with a human body for example. These circuits are adversely affected by an excessively high incoming voltage (or current) from the ESD action. Such an ESD accompanied by an excessive high voltage (or current) causes thin isolation layers of the circuits to be damaged destructively, and/or channels thereof to be shorted, resulting in malfunctions or operational impossibility of integrated circuits. For the purpose of obviating the physical damage, ESD protection units are generally employed in integrated circuits. Such ESD protection units discharge a transient voltage which is excessively high to the outside of an integrated circuit, in order to prevent the transient voltage from being applied to internal circuits of an integrated circuit chip.
The ESD protection units are essential elements for securing stability of semiconductor products. In particular, semiconductor products operating at high frequency and having high integration density especially need high performance ESD protection units. In order to improve the efficiency of ESD protection units, the area provided in a semiconductor product for such an ESD protection unit generally must increase. However, this results in increases in parasitic capacitance. As a result, integration density of a semiconductor chip and current drivability of input/output circuits decrease.
Recently, silicon-controlled rectifiers (SCR) have been considered for protecting integrated circuits from ESD. In an SCR, positive feedback is provided by PNP and NPN bipolar transistors when ESD occurs, thus enhancing discharge capacity. Since hot carrier paths are prevented from concentrating at any local spot, heated-up areas are distributed over the area of the SCR. These features make an SCR very adaptable for protecting integrated circuits from ESD. Such a conventional ESD protection circuit having SCR structure is disclosed in U.S. Pat. No. 5,465,189.
An important functional characteristic of an ESD protection circuit having SCR structure relates to how fast it can be turned (or triggered) on at a desirable voltage. In U.S. Pat. No. 5,455,436, a punch-through voltage (or current) is used as a triggering stimulus, by means of an MOS transistor including source and drain regions which are not structured with an LDD (lightly-doped drain) architecture. In U.S. Pat. No. 5,872,379, a junction breakdown voltage is lowered by forming a low concentration P-type impurity region, overlapped with an N-type well, at a region adjacent to an N+ region in a P-type substrate. The junction breakdown voltage acts as a triggering voltage of the SCR.
While these conventional circuits use a junction breakdown voltage between an N+ region and a P-type substrate, or a punch-through voltage of an MOS transistor, these voltages are marginal factors having a preferred level with a minimum variation of voltage. Therefore, it is substantially difficult for junction breakdown voltage or punch-through voltage to precisely control a trigger voltage of an SCR. Thus, there is a need to control a trigger voltage to be lower and more precise.
The present invention is therefore directed to an electrostatic discharge protection circuit having silicon controlled rectifier structure, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is therefore an object of the present invention to provide an ESD protection unit having SCR structure with a trigger voltage that can be controlled precisely.
The above noted object is fulfilled by an ESD protection unit of the invention that is formed in a semiconductor substrate of first conductivity type, that protects a semiconductor integrated circuit connected to a first node, and that includes a low impurity region of a second conductivity type. A first high impurity region of the first conductivity type is formed in the low impurity region and connected to the first node. A second high impurity region of the second conductivity type is formed in the low impurity region and connected to the first node. A third high impurity region of the second conductivity type is spaced apart from the low impurity region and formed in the semiconductor substrate to be electrically connectable with a second node. A fourth high impurity region of the first conductivity type is formed in the semiconductor substrate and connected to the second node. A fifth high impurity region of the second conductivity type is formed in the low impurity region, and is interposed between the first high impurity region and the third high impurity region. A switch circuit, formed of diode-coupled NMOS transistors, provides a current path from the fifth high impurity region to the second node, when a voltage at the first node reaches a predetermined trigger voltage. A trigger voltage of the ESD protection circuit is dependent on threshold voltages of the NMOS transistors.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.